Method and system for polarity independent step-up converter capable of operating under ultra-low input voltage condition

ABSTRACT

Apparatus and method for a polarity independent step-up converter capable of operating with ultra low input voltage. The step-up converter as disclosed herein receives an input source having a variable polarity and includes a first core circuit coupled to the input source and an output of the step-up converter and a second core circuit coupled to the input source and the output of the step-up converter. The first core circuit is configured to be active for a first input voltage polarity to output a first step-up voltage and the second core circuit is configured to be active for a second input voltage polarity to output a second step-up voltage.

RELATED APPLICATION

The present invention claims priority over U.S. Provisional PatentApplication No. 61/144,216 filed Jan. 13, 2009, and U.S. ProvisionalApplication No. 61/256,628 filed Oct. 30, 2009, the contents of whichare incorporated herein in their entirety.

BACKGROUND

1. Technical Field

The present teaching relates to method and system for analog circuits.More specifically, the present teaching relates to method and system forstep-up converters and systems incorporating the same.

2. Discussion of Technical Background

Step-up DC/DC converters are frequently used to boost a DC input voltageto a higher voltage. A common example is to boost a voltage from asingle 1.5 VDC alkaline cell up to a regulated 3.3 VDC to power, e.g.,analog or digital circuitry in a portable device. Conventionally,step-up converters can operate from input voltages as low as 1V,allowing them to be powered from a single cell. However, there areapplications that must operate from an input voltage significantly lessthan 0.5V. Examples include applications where battery power is notpractical, either due to an inhospitable environment or a remotelocation where having periodical access to replace batteries isimpractical. In those situations, although alternate forms of energy maybe an option to power the electronics, such as photovoltaic (PV) cells,thermopiles, and Peltier cells (also called thermo-electric coolers),these alternative energy sources produce an output voltage well below1V, and in some cases just a few hundred millivolts or less.

Such low input voltages pose a problem for conventional DC/DC convertersbecause they can not start or operate at an input voltage of a fewhundred millivolts or less. One reason for that is that such a low inputvoltage is simply not high enough to forward bias the emitter-basejunction of a transistor, or satisfy the threshold voltage of a typicalMOSFET, making it impossible to power the converter.

Although a higher voltage may be achieved by putting multiple devices inseries, such a solution increases size and cost. Another solution, whichis well documented, is to use a depletion-mode transistor, such as adepletion-mode, N-channel JFET, and a step-up transformer with a highprimary to secondary turns ratio. Since a depletion-mode device conductscurrent with no bias voltage applied to its gate, a free-runningoscillator can be constructed, using the transformer to provide enoughgain to oscillate and step-up the input voltage. Such designs canoperate from an input voltage of 50 mV or less, generating an outputvoltage of several volts or more when a proper transformer turns ratiois provided.

FIG. 1(a) shows such a simplified implementation with a turns ratio of1:100. In this prior art solution, the transformer T1 is connected to apower source 105 and produces an output voltage (SEC) at 140 to be sentto a rectifier. The secondary winding of transformer T1 (115 and 120)provides a sinusoidal output which is used to drive a depletion-modeJFET Q1 (125) on and off. A coupling capacitor 130 provides DC isolationfrom the secondary winding to the gate of 125 because the gate-sourcejunction of Q1 125 clamps the positive peak voltage to a diode dropabove ground. A high value resistor 135 connecting the gate oftransistor 125 to ground provides a DC ground reference. The voltage onthe secondary winding can then be rectified to produce a boosted DCoutput voltage. Typical waveforms observed in circuit 100 are shown inFIG. 1(b), in which waveform 150 represents the voltage observed at thedrain terminal of transistor 125, waveform 160 represents the currentflowing through the drain terminal of transistor 125, and waveform 170represents the voltage 140 at SEC in FIG. 1(a).

For energy sources whose voltage polarity remains constant, the approachdescribed in FIG. 1(a) works well. However, in some applications, thepolarity of the input voltage may be unknown, or may change with time.For example, this situation will occur when a Peltier cell is used asthe energy source. As commonly known, a Peltier cell generates a DCvoltage based on the so-called “Seebeck effect” when a temperaturedifferential is imposed across the cell. Due to the fact that thepolarity of the output voltage of the Peltier cell depends on the“polarity” of the temperature differential across it, the polarity ofthe input voltage to the step-up converter powered by a Peltierdynamically changes. That is, in some applications, the “hot” and “cold”sides of the cell may switch depending on ambient conditions. In thiscase, a step-up converter using a Peltier cell needs to operate witheither polarity input voltage. None of the existing techniques iscapable of operating under such conditions.

The requirements to be “polarity independent” and the ability to operatefrom a very low input voltage of either polarity pose a major challengeto the prior art. All existing step-up converters, including the onesthat can work with low input voltages, cannot start or operate if thewrong DC polarity is applied to their inputs.

SUMMARY

The present teaching relates to polarity independent step-up convertercapable of operating under ultra-low input voltage conditions. In someexemplary embodiments, a step-up converter connecting to an input sourcehaving a variable polarity comprises a step-up transformer including aprimary winding and two secondary windings coupled to the input source,a first depletion mode transistor coupled at one of its terminals to theinput source and at another one of its terminals to a reference point,and a second depletion mode transistor coupled at its first terminal tothe primary winding and at its second terminal to the reference point.

According to some aspects of the present teaching, each of the twosecondary windings is capacitively coupled to first and second diodecharge pump circuits, respectively. The outputs of the first and seconddiode charge pump circuits are then combined to generate an output ofthe step-up converter.

In some other embodiments, a step-up converter connecting to an inputsource having a variable polarity comprises a first core circuit and asecond core circuit. The first core circuit is coupled to the inputsource and an output of the step-up converter and is configured to beactive for a first input voltage polarity to output a first step-upvoltage. The second core circuit is coupled to the input source and theoutput of the step-up converter and is configured to be active for asecond input voltage polarity to output a second step-up voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventions claimed and/or described herein are further described interms of exemplary embodiments. These exemplary embodiments aredescribed in detail with reference to the drawings. These embodimentsare non-limiting exemplary embodiments, in which like reference numeralsrepresent similar structures throughout the several views of thedrawings, and wherein:

FIG. 1(a) (Prior Art) shows a simplified prior art step-up converter;

FIG. 1(b) shows waveforms observed at different points of the circuit asdepicted in FIG. 1(a);

FIG. 2(a) depicts an exemplary circuit for a polarity independent andultra low input voltage step-up converter, according to an embodiment ofthe present teaching;

FIG. 2(b) shows waveforms observed at different points of the circuit asdepicted in FIG. 2(a), according to an embodiment of the presentteaching;

FIG. 2(c) shows a different exemplary circuit for a polarity independentand ultra low input voltage step-up converter, according to anembodiment of the present teaching;

FIG. 3 depicts another exemplary circuit for a polarity independent andultra low input voltage step-up converter, according to an embodiment ofthe present teaching;

FIGS. 4-7 show different waveforms observed at different points of thecircuit as depicted in FIG. 3, according to an embodiment of the presentteaching; and

FIGS. 8-11 show different waveforms observed at different points of thecircuit as depicted in FIG. 3, according to an embodiment of the presentteaching.

DETAILED DESCRIPTION

Circuits for polarity independent step-up converter capable of operatingunder ultra-low input voltage conditions are disclosed. The presentteaching is to solve the problem existing in the prior art technologies.In FIG. 2(a), an exemplary circuit 200 is shown according to anembodiment of the present teaching. Circuit 200 comprises an inputvoltage source 205, a transformer T1 including one first winding 210 andtwo secondary windings 215 and 220, two depletion mode devices 225 and240, and additional components such as resistors 235 and 250 andcapacitors 230 and 245.

The circuit 200 is designed to operate with either polarity inputvoltage. The input voltage source 205 provides an input voltage that canbe of either polarity. In some embodiments, each of the two secondarywindings of transformer T1, 215 and 220, has a similar turns ratio,e.g., 1:100 from primary to secondary. A grounded center-tap between thewindings provides secondary voltages of equal amplitude but oppositephase. Although 1:100 is used herein as an example, it is understoodthat the primary to secondary turns ratio can be adjusted to a valuebased on the input voltage required in the application.

As seen in FIG. 2(a), two depletion-mode devices (Q1 240 and Q2 225) areemployed in series, between the input source and the primary winding oftransformer T1. Note that the input voltage source, as compared to FIG.1(a), is no longer ground referenced. The gate of depletion mode device225 is coupled to the secondary winding 220 via capacitor 230, which isserially connected to resistor 235 to the ground. At the other terminalof capacitor 230, where it connects to the secondary winding 220, anoutput voltage SEC2 260 is provided to a rectifier. The gate ofdepletion mode device 240 is coupled to secondary winding 215 viacapacitor 245, which is serially connected to resistor 250 to theground. At the other terminal of capacitor 245, where it connects to thesecondary winding 215, an output voltage SEC1 255 is provided to therectifier.

The depletion-mode devices 225 and 240 are driven by the opposite phasesof T1's center-tapped secondary winding. When the input voltage is firstapplied, both Q1 240 and Q2 225 conduct because their gates are both atzero volts. The circuit 200 begins to oscillate because the negativegate threshold voltage of each transistor allows for an overlap in theconduction times of Q1 240 and Q2 225. As the secondary voltagesincrease in amplitude during each cycle, one transistor is turned onharder as the other transistor is turned off. During the overlapconduction time, current flows from the input source through Q1 240 andQ2 225 and the primary winding of T1. Note that since the circuit isfully symmetrical, the input voltage can be of either polarity and thecircuit 200 will operate in the same manner, making it polarityindependent. In some embodiments, the depletion mode JFETs (Q1 240 andQ2 225) can also be implemented using depletion mode NMOS devices.

FIG. 2(b) shows different signals observed at different points of thecircuit 200. For example, when input voltage is applied, the currentobserved at the drain terminal of transistor Q1 240 (waveform 270) isbetween zero and 1.0 mA corresponding to a certain portion of the inputphase. Waveforms 275 and 280 correspond to the voltages observed at thedrain terminals of the two transistors, respectively. Waveform 285corresponds to the output voltage observed at SEC2 260 and waveform 290corresponds to the output voltage observed at SEC1 255.

The circuit as illustrated in FIG. 2(a) may also be capacitively coupledto diode charge pump circuits. One such embodiment is illustrated inFIG. 2(c). Specifically, circuit 251 is similarly constructed as circuit200 except that SEC1 255 is capacitively coupled to, via capacitor 252,a diode charge pump comprising diodes 256 and 257 and SEC2 260 iscapacitively coupled to, via capacitor 267, another charge diode chargepump comprising diodes 259 and 261. The outputs of the respective diodecharge pump circuits are combined at node Vout 267. In this illustratedembodiment, Vout is decoupled with a 1 uF filter capacitor 262 andlimited to approximately 5V by a Zener diode 265.

Another exemplary circuit 300 is shown in FIG. 3. In this exemplaryembodiment, there are two transformers employed with similar turnsratios, e.g., 1:100, illustrated by L1 and L3 (313 and 317) and L2 andL4 (345 and 349), respectively. Coupled with each of the transformersare two sets of MOSFET transistors connected in parallel. As illustratedin FIG. 3, the first set of MOSFET transistors M1 311 and M5 309 as wellas the second set of MOSFET transistors M3 341 and M6 339 are coupledwith the transformer including the primary winding L1 313 and secondarywinding L3 317 via the transformer coupling coefficient and capacitor C2323, which is a gate drive coupling capacitor. The transformer couplingcoefficient is typically between 0.95 and 0.99. A coupling coefficientof 1.0 represents an ideal transformer. This forms the core of theUltra-Low voltage converter when the input voltage supplied by VTEG1 303is a positive polarity.

Similarly, another two sets of MOSFET transistors are coupled to atransformer modeled by the primary winding L2 345 and secondary windingL4 349. Specifically, the first set of MOSFET transistors M2 361 and M8359 as well as the second set of MOSFET transistors M4 365 and M7 363are coupled with L2/L4 transformer with a certain coupling coefficientand C9 353 which is another gate drive coupling capacitor. This formsthe core of the Ultra-Low voltage converter when the input voltagesupplied by Thermo Electric Generator 1 (or VTEG1) 303 is a negativepolarity.

Both core ultra-low voltage circuits are capacitively coupled to theircorresponding diode charge pump circuits, respectively. Specifically,the top ultra-low voltage circuit for the positive polarity converter iscapacitively coupled to a charge pump comprising diodes D5 337 and D6335. The bottom ultra-voltage circuit for the negative polarityconverter is capacitively coupled to its charge pump comprising diodesD1 373 and D4 375. The outputs of the respective diode charge pumpcircuits are combined at the node VOUT 380. In the illustratedembodiment, VOUT is decoupled with a 1 uF filter capacitor 377 andlimited to approximately 5V by a Zener diode, D11 379.

The Thermo Electric Generator (VTEG1) and its associated seriesresistance represented by (RTEG) 305 form an electrical model of theThermal Electric Generator power source suitable for computersimulation. There are other components in circuit 300 and theirfunctionalities are the following. Resistors R1/R2 (315/307) and R3/R5(347/343) correspond to the parasitic winding resistances of therespective transformers. Capacitor C8 301 is an input decouplingcapacitor connected across the Thermal Electric Generator (TEG) voltagesource to minimize the effects of voltage ripple in the input.Capacitors C1 319 and C3 355 model the parasitic interwindingcapacitances of the respective transformers. Diodes D2/D10 (327/329) andD3/D9 (367/371) are Zener diode clamps to prevent an over voltage of thegate-sources of the MOSFET power switches.

Although resistor 331 is shown in the illustrative embodiment, it wasadded for simulation purposes. In practice, resistor 331 does not needto be present. Resistors 333 and 369 provide a DC termination to groundfor the respective MOSFET power transistors. Resistors 325 and 357provide current limiting for the Zener diode clamps (D3 367, D9 371, D2327, D10 329), although they may not be critical to the normal operationof the circuit.

Given an input voltage polarity, only one of the core circuits isactive. The circuit 300 as shown in FIG. 3, begins to deliver power tothe load at an input voltage of approximately +/−21 mV. If largergeometry transistors are employed (MN1,2,3,4), the typical startupvoltage can be lower. Below, a detailed description of the circuitoperation is provided. Since circuit operation is identical for each ofthe positive and negative core circuits, the discussion herein focuseson the negative polarity converter (bottom half of circuit 300 in FIG.3). Operation of the positive polarity core is identical, when apositive voltage is applied.

FIGS. 4 to 7 show the initial converter startup as the input voltageprovided by VTEG1 slowly increases from 0V. Specifically, in FIG. 4, thetop plot shows the input voltage provided at the VTEG 303. The middleplot depicts the voltage (see waveform 420) measured at the gateterminal of transistor M2 361 (GATE2) at the start point of theconverter as well as the primary current (430) measured at L2 345. Thebottom plot in FIG. 4 depicts the output voltage (440) measured at VOUT380. FIG. 5 provides similar plots, where plot 510 corresponds to 410,plot 540 corresponds to 440, 530 corresponds to 420, with an exceptionthat plot 520 corresponds to the voltage observed at the secondarywinding at point SEC2 in FIG. 3. FIG. 6 also provides plots related tothe initial startup process, where plot 610 corresponds to 410, and plot640 corresponds to plot 440. In FIG. 6, voltages observed at GATE1 andGATE2, respectively, are plotted as 620 and 630 and it can be seen thatwhen GATE2 in the bottom core circuit is active (see plot 620), GATE1 ofthe top core circuit is inactive (see plot 630). FIG. 7 provides anothervariation in depicting the initial startup process, in which plot 710corresponds to plot 410 and plot 740 corresponds to plot 440, where thetwo plots in the middle represent the voltage observed at GATE2 (730)and the voltage observed at the drain terminal of transistor M2 361.

In FIG. 4, it can be seen that the negative polarity core circuit beginsto self-oscillate at an input voltage of approximately 21 mV. Duringsuch an initial startup, only the depletion mode MOSFETs, M2 361 and M4365 are conducting, due to the very low voltage across the gate to thesource. This can be seen in the voltage waveform 420 plotted based onthe observed voltage at the gate 2 terminal (see gates of MOSFETs M2 361and M4 365 in FIG. 3). This is due to the depletion mode MOSFETs havinga typical threshold voltage of approximately −0.5V, while the thresholdvoltage for standard MOSFETS is about 0.75V.

As can be seen in FIG. 3, with a sufficient voltage on VTEG1, MOSFETtransistors M2 361 and M4 365 bridge the transformer primary, L2 345,across VTEG1 with M4 365 providing the return path for VTEG1 and M2 361driving one side of the primary winding and VTEG1 driving the oppositeside of the primary winding. A qualitative description of the oscillatoris provided herein. The voltage on the gate terminal of M2 361 (GATE2)is phase shifted by 180 degrees at the drain of transistor M2 361 due toits common source amplifier configuration. This phase shifted voltage isapplied across the primary of the transformer, L2 345, as describedabove. The transformer couples this signal to its secondary, L4 349.Because the secondary or magnetizing inductance of the transformer actsupon the effective secondary capacitance comprised of the MOSFET inputcapacitance and transformer winding capacitance, it imposes anadditional 180 degree phase shift at the resonant frequency of thecircuit. To sustain oscillation, both a positive feedback (360 degreephase shift) and a loop gain that is greater than unity are required.Both of these conditions are satisfied when the input voltage from VTEG1is high enough to bring the depletion mode MOSFET M2 361 out of thelinear region of operation, which is characterized by very low gain toits saturated region, characterized by high gain.

Once the circuit begins to oscillate, the coupling capacitor, C10 351connected on one side to SEC2 and on its other side to diode charge pumpD1 373 and D4 375 transfers current to VOUT 380 via D4 375 when theoscillation polarity is positive and recharges C10 351 via D1 373 whenthe oscillation voltage polarity is negative. The steady state voltageacross C10 351 is approximately equal to ½ the p-p amplitude of theoscillating waveform seen on the transformer secondary, SEC2. Theoscillation amplitude observed at SEC2 is a function of the voltageapplied to the transformer primary, which is, e.g., in an idealsituation VTEG1 and the transformer turns ratio, 100:1 in theillustrated embodiment. It is understood that other transformer ratioscan also be used.

In general, a lower turns ratio requires a higher startup voltage butwill deliver greater power with a larger Vin applied, while the higherturns ratio will allow for lower startup voltages, but lower outputpower at higher input voltages. FIGS. 8-11 show waveforms observed atthe gate terminal (GATE2) of transistor M2 361 and gate terminal (GATE1)of transistor M1 311 in circuit 300 when an instantaneous +/−100 mVinput voltage is applied. Zener clamps D3/D9 (367/371) and D2/D10(327/329) limit the voltages at those gate terminals (GATE1 and GATE2)to approximately +/−5V, which is required by the particular IC processemployed. It is to be noted that when GATE2 is active, GATE1 is notactive and when the voltage polarity is switched, the opposite occurs.As the gate drive increases, the converter pulls more current from theinput voltage source, VTEG1 303.

This can be seen in FIG. 8, where when the VTEG switches from an inputvoltage of −100 mV to +100 mV (see plot 810), transistor M2 361 switchesfrom active to inactive (see plot 820) and transistor M1 311 switchesfrom inactive to active (see plot 830). The voltage measured at GATE2 islimited by the Zener diode clamp to about +/−5V (820) and so is thevoltage measured at GATE1 (830). The VOUT measured at 380 remains at itsregulated value of 5V, regardless of the input voltage polarity appliedto the converter. (see plot 840).

FIG. 9 shows the input and output voltage relationship as well asvoltages observed at different points within circuit 300. Waveform 910represents the input voltage with a certain polarity. Waveform 950represents the output voltage VOUT 380. As can be seen, the outputvoltage exhibits a small 1.4 mV peak to peak ripple riding on thenominal 5V DC at the oscillation frequency of the converter. Waveform920 represents the primary voltage of transformer L2, waveform 930represents the secondary voltage observed at SEC2, and waveform 940represents the gate drive voltage observed at GATE2.

FIG. 10 similarly shows the output voltage waveform 1070 as well as thevoltage waveforms 1050 and 1060 based on voltages observed at GATE2 andSEC2, respectively. Waveform 1020 represents the current observed at thedrain terminal of depletion mode device M4 365 displayed in comparisonwith the magnitude of the drain current in the standard threshold MOSFETt 1010 of transistor M7 363, once the circuit 300 is in regulation witha sufficient gate drive. Similarly, Waveform 1040 represents the currentobserved at the drain terminal of the parallelly connected depletionmode device M2 361 displayed in comparison with the magnitude of draincurrent in the standard MOSFET threshold 1030 of transistor M8 359 whenthe circuit 300 is in regulation with a sufficient gate drive.

In FIG. 11, in addition to the similar plots (output voltage 1170 andvoltage waveforms 1150 and 1160 representing the voltages observed atGATE2 and SEC2) as those shown in FIGS. 9 and 10, the top two plotsdisplay the relative magnitude of the standard threshold MOSFETs forboth halves of the converter when the output voltage is in regulation.Note how the drain currents of M8 359 and M6 339 (the non-active) sidein this simulation are essentially zero.

In the illustrated embodiment, VTEG1 is modeled with a 1.5 ohm sourceresistance, as a result, the actual voltage applied across the primaryis reduced and the resulting gate drive voltage is reducedproportionally to about +/−3.5 V seen after the circuit has been inoperation by ˜20 mS. With non-zero source impedance devices, such asThermal Electric Generators (TEG), it may be desirable to match theinput resistance of the power converter to the source resistance of theTEG in order to extract the maximum available power. The naturalnegative feedback characteristic as shown here, although not perfect,tends to keep the power converter operating near the optimum point formaximum power transfer.

While the inventions have been described with reference to the certainillustrated embodiments, the words that have been used herein are wordsof description, rather than words of limitation. Changes may be made,within the purview of the appended claims, without departing from thescope and spirit of the invention in its aspects. Although theinventions have been described herein with reference to particularstructures, acts, and materials, the invention is not to be limited tothe particulars disclosed, but rather can be embodied in a wide varietyof forms, some of which may be quite different from those of thedisclosed embodiments, and extends to all equivalent structures, acts,and, materials, such as are within the scope of the appended claims.

We claim:
 1. A voltage step-up converter comprising: an input sourcehaving a variable polarity; a single step-up transformer including aprimary winding and two secondary windings, wherein the primary windingis coupled to the input source; a first depletion mode transistorcoupled at its first terminal to the input source and at its secondterminal to a reference point; and a second depletion mode transistorcoupled at its first terminal to the primary winding and at its secondterminal to the reference point; a coupling capacitor between the firstdepletion mode transistor and a second winding of the secondary winding;and a second coupling capacitor between the second depletion modetransistor and a first winding of the secondary winding, wherein thestep-up converter is polarity independent.
 2. The step-up converter ofclaim 1, wherein the input source includes Peltier cells.
 3. The step-upconverter of claim 1, wherein the two secondary windings of the singlestep-up transformer have a certain turns ratio from primary tosecondary.
 4. The step-up converter of claim 1, wherein the firstdepletion mode transistor and the second depletion mode transistorinclude N-channel JFET.
 5. The step-up converter of claim 1, wherein thefirst depletion mode transistor and the second depletion mode transistorare each configured to conduct current with no bias voltage applied totheir gate terminals.
 6. The step-up converter of claim 1, wherein thegate terminal of the first depletion mode transistor is coupled to oneterminal of the two secondary windings and the gate terminal of thesecond depletion mode transistor is coupled to an opposite terminal ofthe two secondary windings.
 7. The step-up converter of claim 1, whereinthe output of the step-up converter is coupled to a rectifier circuit.8. The step-up converter of claim 6, wherein each one terminal of thetwo secondary windings is capacitively coupled to first and second diodecharge pump circuits, respectively.
 9. The step-up converter of claim 8,wherein the outputs of the first and second diode charge pump circuitsare combined to generate an output of the step-up converter.
 10. Thestep-up converter of claim 8, wherein the first charge pump circuitcomprises: serially connected first and second diodes wherein anode ofthe first diode is connected to the ground and cathode of the firstdiode is connected with anode of the second diode, cathode of the seconddiode is connected to the output of the step-up converter, and oneterminal of the first secondary winding is capacitively connected to thecathode of the first and anode of the second diode.
 11. The step-upconverter of claim 8, wherein the second charge pump circuit comprises:serially connected third and fourth diodes wherein anode of the thirddiode is connected to the ground and cathode of the third diode isconnected to anode of the fourth diode, cathode of the fourth diode isconnected to the output of the step-up converter, and one terminal ofthe second secondary winding is capacitively connected to the cathode ofthe third and anode of the fourth diode.
 12. The step-up converter ofclaim 10 or 11, wherein the diodes in the first and second charge pumpcircuits are replaced with low loss MOSFET switches to improve overallconversion efficiency.
 13. A polarity independent, ultra-low inputvoltage step-up converter comprising: an input source having a variablepolarity; a first core circuit coupled to the input source and an outputof the step-up converter, configured to be active for a first inputvoltage polarity to output a first step-up voltage; a second corecircuit coupled to the input source and the output of the step-upconverter, configured to be active for a second input voltage polarityto output a second step-up voltage; and charge pump circuitry configuredto maintain the first core circuit inactive when the second core circuitis active, and to maintain the second core circuit inactive when thefirst core circuit is active; wherein the first core circuit comprises:a first step-up transformer including a first primary winding and afirst secondary winding coupled to the input source; a first depletionmode transistor coupled at its first terminal to the input source and atits second terminal to a reference point; and a second depletion modetransistor coupled at its first terminal to the primary winding and atits second terminal to the reference point.
 14. The step-up converter ofclaim 13, wherein the input source includes Peltier cells.
 15. Thestep-up converter of claim 13, wherein the first secondary winding has acertain turns ratio from primary to secondary.
 16. The step-up converterof claim 13, wherein the gate terminals of the first and seconddepletion mode transistors are coupled to the first secondary winding.17. The step-up converter of claim 13, further comprising: a firsttransistor connected in parallel with the first depletion modetransistor; and a second transistor connected in parallel with thesecond depletion mode transistor, wherein the first and secondtransistors are configured to enhance power delivery capability of thefirst core circuit.
 18. The step-up converter of claim 17, wherein thefirst and second transistors are N-channel MOSFETs.
 19. The step-upconverter of claim 18, wherein the N-channel MOSFETs have a positivethreshold voltage.
 20. The step-up converter of claim 13, wherein thesecond core circuit comprises: a second step-up transformer including asecond primary winding and a second secondary winding coupled to theinput source; a third depletion mode transistor coupled at its firstterminal to the input source and at its second terminal to a referencepoint; and a fourth depletion mode transistor coupled at its firstterminal to the primary winding and at its second terminal to thereference point.
 21. The step-up converter of claim 20, wherein thesecond secondary winding has a certain turns ratio from primary tosecondary.
 22. The step-up converter of claim 20, wherein the gateterminals of the third and fourth depletion mode transistors are coupledto the second secondary winding.
 23. The step-up converter of claim 20,further comprising: a third transistor connected in parallel with thethird depletion mode transistor; and a fourth transistor connected inparallel with the fourth depletion mode transistor, wherein the thirdand fourth transistors are configured to enhance power deliverycapability of the second core circuit.
 24. The step-up converter ofclaim 20, wherein the third and fourth transistors are N-channelMOSFETs.
 25. The step-up converter of claim 24, wherein the N-channelMOSFETs have a positive threshold.
 26. The step-up converter of claim 13or claim 20, wherein the depletion mode transistors include N-channelJFETs.
 27. The step-up converter of claim 13 or claim 20, wherein thedepletion mode transistors are each configured to conduct current withno bias voltage applied to their gate terminals.
 28. The step-upconverter of claim 13, wherein the charge pump circuitry comprises: theoutput of the first core circuit being capacitively coupled to a firstdiode charge pump circuit; and the output of the second core circuitbeing capacitively coupled to a second diode charge pump circuit. 29.The step-up converter of claim 28, wherein the outputs of the first andsecond diode charge pump are combined to generate an output of thestep-up converter.
 30. The step-up converter of claim 28, wherein thefirst charge pump circuit comprises: serially connected first and seconddiodes wherein anode of the first diode is connected to the ground andcathode of the first diode is connected with anode of the second diode,cathode of the second diode is connected to the output of the step-upconverter, and the output of the first core circuit is connected to thecathode of the first and anode of the second diodes.
 31. The step-upconverter of claim 28, wherein the second charge pump circuit comprises:serially connected third and fourth diodes wherein anode of the thirddiode is connected to the ground and cathode of the third diode isconnected to anode of the fourth diode, cathode of the fourth diode isconnected to the output of the step-up converter, and the output of thesecond core circuit is connected to the cathode of the third and anodeof the fourth diodes.
 32. The step-up converter of claim 30 or 31,wherein the diodes in the first and second charge pump circuits arereplaced with low loss MOSFET switches to improve overall conversionefficiency.